Overview

In this tutorial, we’ll discuss the TMS320 PWM generation. You’ll get to know how the PWM signal is generated, how to control its frequency, duty cycle, and how to estimate the PWM resolution.

Introduction

This chapter includes an overview and information about each submodule

Required Hardware Components

Hardware

  • Launchxl-f28379d
  • Push button
  • Led

Software:

  • Code Composer Studio

Configuring Device Pins

To connect the device input pins to the module, the Input X-BAR must be used. Some examples of when an external signal may be needed are TZx, TRIPx, and EXTSYNCIN. Any GPIO on the device can be configured as an input. The GPIO input qualification should be set to the asynchronous mode by setting the appropriate GPxQSEL register bits to 11b. The internal pullups can be configured in the GPyPUD register. Since the GPIO mode is used, the GPyINV register can invert the signals. Additionally, some TRIPx (TRIP4-12 excluding TRIP6) signals must be routed through the ePWM X-Bar in addition to the Input XBar.

The GPIO mux registers must be configured for this peripheral. To avoid glitches on the pins, the GPyGMUX bits must be configured first (while keeping the corresponding GPyMUX bits at the default of zero), followed by writing the GPyMUX register to the desired value. See the GPIO chapter for more details on GPIO mux, GPIO settings, and XBAR configuration.

ePWM Modules Overview

Eight submodules are included in every ePWM peripheral. Each of these submodules performs specific tasks that can be configured by software.

Table 15-1 lists the eight key submodules together with a list of their main configuration parameters. For example, if you need to adjust or control the duty cycle of a PWM waveform, then you should see the counter-compare submodule in Section 15.5 for relevant details.

Submodule Configuration

PWM Submodule

  • • Time-Base Submodule
  • • Counter Compare Submodule
  • • Action Qualifier Submodule
  • • Dead-Band Generator Submodule
  • • PWM Chopper (PC) Submodule
  • • Trip Zone Submodule
  • • Event Trigger Submodule
  • • Digital Compare Submodule

The ePWM Type 4 is functionally compatible with Type 2 (a Type 3 does not exist). Type 4 has the following enhancements in addition to the Type 2 features:

Register Address Map

Additional registers are required for new features on ePWM Type 4. The ePWM register address space has been remapped for better alignment and easy usage.

Delayed Trip Functionality

Changes have been added to achieve Deadband insertion capabilities to support, for example, delayed trip functionality needed for peak current mode control type application scenarios. This has been accomplished by allowing comparator events to go into the Action Qualifier as a trigger event ( Events T1 and T2 ). If comparator T1 / T2 events are used to edit the PWM, changes to the PWM waveform will not take place immediately. Instead, they will synchronize to the next TBCLK.

Dead-Band Generator Submodule Enhancements

Shadowing of the DBCTL register to allow dynamic configuration changes.

One Shot and Global Load of Registers

The ePWM Type 4 allows one shot and global load capability from shadow to active registers to avoid partial loads in, for example, multi-phase applications. It also allows a programmable prescale of shadow to active load events. ePWM Type 4 Global Load can simplify ePWM software by removing interrupts and ensuring that all registers are loaded at the same time.

Trip Zone Submodule Enhancements

Independent flags have been added to reflect the trip status for each of the TZ sources. Changes have been made to the trip zone submodule to support certain power converter switching techniques like valley switching.

Digital Compare Submodule Enhancements

Blanking window filter register width has been increased from 8 to 16 bits. DCCAP functionality has been enhanced to provide more programmability.

The ePWM Type 4 allows PWM SYNCOUT generation based on CMPC and CMPD events. These events can also be used for PWMSYNC pulse selection.

The ePWM Type 2 is fully compatible with Type 1. Type 2 has the following enhancements in addition to the Type 1 features:

High Resolution Dead-Band Capability

High-resolution capability is added to dead-band RED and FED in half-cycle clocking mode.

Dead-Band Generator Submodule Enhancements

The ePWM Type 2 has features to enable both RED and FED on either PWM output. Provides increased dead band with 14-bit counters and dead-band / dead-band high-resolution registers are shadowed

High Resolution Extension available on ePWMxB outputs

Provides the ability to enable high-resolution period and duty cycle control on ePWMxB outputs.

Counter Compare Submodule Enhancements

The ePWM Type 2 allows Interrupts and SOC events to be generated by additional counter compares CMPC and CMPD.

Event Trigger Submodule Enhancements

Prescaling logic to issue interrupt requests and ADC start of conversion expanded up to every 15 events. It allows software initialization of event counters on SYNC events.

Digital Compare Submodule Enhancements

Digital Compare Trip Select logic [DCTRIPSEL] has up to 12 external trip sources selected by the Input X-BAR logic in addition to an ability to OR all of them (up to 14 [external and internal sources]) to create the respective DCxEVTs.

Simultaneous Writes to TBPRD and CMPx Registers

This feature allows writes to TBPRD, CMPA: CMPAHR, CMPB: CMPBHR, CMPC and CMPD of any ePWM module to be tied to any other ePWM module, and also allows all ePWM modules to be tied to a particular ePWM module if desired.

Shadow to Active Load on SYNC of TBPRD and CMP Registers

This feature supports simultaneous writes of TBPRD and CMPA/B/C/D registers.

ePWM Electrical Data and Timing

ePWM Switching Characteristics

TBPRD Register (Offset = 63h) [reset = 0h]

TBPHS Register (Offset = 60h) [reset = 0h]

TBCTR Register (Offset = 4h) [reset = 0h]

TBCTL Register (Offset = 0h) [reset = 83h]

AQCTLA Register (Offset = 40h) [reset = 0h]

Calculate the PWM duty cycle



Calculate total time
 
T1= On time 20ms
T2 = Off Time 5ms
Total time = T1+T2 = 20+5 = 25ms
Convert in sec = Total time /1000 = 25/1000 = 0.025sec
 
Calculate frequency
Frequency(F) = 1/Total Time
F = 1/0.025  =  40 HZ
 
Calculate duty cycle
Calculate duty cycle = (PWM_ON_Time/PWM_Total_time))%100
Duty cycle         =            20/25%100       =80%

In My Case

TBCLK = EPWMCLK / (HSPCLKDIV x CLKDIV).

EPWMCLK = 1200 TBCLKSYNC clock
HSPCLKDIV = 1
CLKDIV = 1

SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

Total Time = On time+OFF Time
= 4us+4us
= 8us
Convert into sec
= 8/1000000
= 0.000 008sec
Calculate frequency

Frequency (F) = 1/Total time
= 1/0.000 008
= 125000
Convert in to khz
= 125000/1000
= 125khz

Calculating PWM Period and Frequency

The frequency of PWM events is controlled by the time-base period (TBPRD) register and the mode of the time-base counter. Figure 15-6 shows the period (Tpwm) and frequency (Fpwm) relationships for the upcount, down-count, and up-down-count time-base counter modes when the period is set to 4 (TBPRD = 4). The time increment for each step is defined by the time-base clock (TBCLK) which is a prescaled version of the ePWM clock (EPWMCLK).

The time-base counter has three modes of operation selected by the time-base control register (TBCTL):

Up-Down-Count Mode:

In up-down-count mode, the time-base counter starts from zero and increments until the period (TBPRD) value is reached. When the period value is reached, the time-base counter then decrements until it reaches zero. At this point the counter repeats the pattern and begins to increment.

Up-Count Mode:

In this mode, the time-base counter starts from zero and increments until it reaches the value in the period register (TBPRD). When the period value is reached, the time-base counter resets to zero and begins to increment once again.

Down-Count Mode:

In down-count mode, the time-base counter starts from the period (TBPRD) value and decrements until it reaches zero. When it reaches zero, the time-base counter is reset to the period value and it begins to decrements once again.

FINAL CODE

include "F28x_Project.h"
#include "F2837xD_device.h"
#include "F2837xD_Examples.h"
#include "driverlib.h"
#include "device.h"
//
// Function Prototypes
//
void initEPWM1(void);
void PinMux_init();

void main(void)
{
    //
    // Initialize device clock and peripherals
    //
    Device_init();

    //
    // Disable pin locks and enable internal pull-ups.
    //
    Device_initGPIO();

    //
    // Initialize PIE and clear PIE registers. Disables CPU interrupts.
    //
    Interrupt_initModule();

    //
    // Initialize the PIE vector table with pointers to the shell Interrupt
    // Service Routines (ISR).
    //
    Interrupt_initVectorTable();

    //
    // Interrupts that are used in this example are re-mapped to ISR functions
    // found within this file.
    //
//    Interrupt_register(INT_EPWM1_TZ, &epwm1TZISR);


    //
    // Configure ePWM1, ePWM2, and TZ GPIOs
    //
    PinMux_init();

    //
    // Disable sync(Freeze clock to PWM as well)
    //
    SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

    //
    // Initialize ePWM1 and ePWM2
    //
    initEPWM1();


    //
    // Enable sync and clock to PWM
    //
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
    //
    // Enable Global Interrupt (INTM) and real time interrupt (DBGM)
    //
    EINT;
    ERTM;



    while(1){

    }
}

//
// initEPWM1 - Configure ePWM1
//
void initEPWM1()
{

        EPwm1Regs.TBPRD = 2000;       // Set timer period 801 TBCLKs
        EPwm1Regs.TBPHS.bit.TBPHS = 0x0000;        // Phase is 0
        EPwm1Regs.TBCTR = 0x0000;
       // Set Compare values
        EPwm1Regs.CMPA.bit.CMPA = 1000;    // Set compare A value
      // Setup counter mode
       EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
       EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;        // Disable phase loading
       EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
       EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

       EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;            // Set PWM1A on event A, up
      // count
       EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;          // Clear PWM1A on event A,
                                                    // down count

}


void PinMux_init()
{
    EALLOW;
    //EPWM1 -> myEPWM1 Pinmux
    GpioCtrlRegs.GPAMUX1.all=0;// gpio 15 to gpio 0 a;; general purpouse I/O
    GpioCtrlRegs.GPAMUX1.bit.GPIO0=1;// epwm active
    EDIS;

}

Output Wave Forms

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