Table of Contents
Overview
PWM (Pulse Width Modulation) is a method of controlling the average voltage. It is a current of voltage pulses that reduces the electrical power supplied by the electrical signal. The effective voltage is monitored by displaying individual pulses in the PWM signal voltage pulse current.
A PWM signal consists of two main components that define its behaviour: a duty cycle and a frequency.
Basic Principle of PWM
Pulse width modulation is basically a square wave with a variable high and low time. A basic PWM signal is shown in the figure below.
- On-Time − Duration of time signal is high.
- Off-Time − Duration of time signal is low.
- Period − It is represented as the sum of on-time and off-time of PWM signal.
- Duty Cycle − It is represented as the percentage of time signal that remains on during the period of the PWM signal.
Period
As shown in the figure, Ton indicates the turn-on time and Toff indicates the turn-off time of the signal. The period is the sum of the on and off times and is calculated as shown in the following equation:
T_total = T_on+T_off
Duty cycle
The term duty cycle describes the ratio of time “in” to the normal interval or “period” of time; A lower duty cycle corresponds to a lower power because the power is off most of the time. The duty cycle is expressed as a percentage, 100% fully operational. When the digital signal is on half the time and off the other half of the time, the digital signal has a 50% duty cycle and is similar to a “square wave”. When a digital signal spends more time in the on the state than in the off state, its duty cycle is over 50%. When a digital signal spends more time in the off state than it does in the on state, it has a duty cycle of less than 50%. Here is an image that illustrates these three scenarios:
Frequency of Signal
The signal frequency determines how quickly the PWM will complete a cycle (i.e. 1000 Hz would be 1000 cycles per second), which means how quickly to switch between the on (high) and off (low) states. By repeating this ON-OFF pattern at a fast enough rate and a certain duty cycle, the output will appear to behave like a constant voltage analog signal when the devices are turned on.
Example: If we want to generate a 2V analog signal for a given digital source that can be high (on) at 5V or low (off) at 0V, we can use PWM with a 40% duty cycle. It will save the 5V output 40% of the time. If the digital signal is spinning fast enough, the voltage visible at the output appears to be the average voltage. If the digital drop is 0 volts (which often happens), the average voltage can be calculated by multiplying the digital high voltage by the duty cycle, or 5 volts x 0.4 = 2 volts.
Other PWM Applications
There are other applications that use PWM technology, including:
- buzzer motor of different size
- Check engine speed
- servo direction control
- Provide analog output
- generate an audio signal
- Telecommunication: message encryption
Configuring Device Pins
To connect the device input pins to the module, the Input X-BAR must be used. Some examples of when an external signal may be needed are TZx, TRIPx, and EXTSYNCIN. Any GPIO on the device can be configured as an input. The GPIO input qualification should be set to the asynchronous mode by setting the appropriate GPxQSEL register bits to 11b. The internal pullups can be configured in the GPyPUD register. Since the GPIO mode is used, the GPyINV register can invert the signals. Additionally, some TRIPx (TRIP4-12 excluding TRIP6) signals must be routed through the ePWM X-Bar in addition to the Input XBar.
The GPIO mux registers must be configured for this peripheral. To avoid glitches on the pins, the GPyGMUX bits must be configured first (while keeping the corresponding GPyMUX bits at the default of zero), followed by writing the GPyMUX register to the desired value. See the GPIO chapter for more details on GPIO mux, GPIO settings, and XBAR configuration.
ePWM Modules Overview
Eight submodules are included in every ePWM peripheral. Each of these submodules performs specific tasks that can be configured by software.
Table 15-1 lists the eight key submodules together with a list of their main configuration parameters. For example, if you need to adjust or control the duty cycle of a PWM waveform, then you should see the counter-compare submodule in Section 15.5 for relevant details.
Submodule Configuration
PWM Submodule
- • Time-Base Submodule
- • Counter Compare Submodule
- • Action Qualifier Submodule
- • Dead-Band Generator Submodule
- • PWM Chopper (PC) Submodule
- • Trip Zone Submodule
- • Event Trigger Submodule
- • Digital Compare Submodule
The ePWM Type 4 is functionally compatible with Type 2 (a Type 3 does not exist). Type 4 has the following enhancements in addition to the Type 2 features:
Register Address Map
Additional registers are required for new features on ePWM Type 4. The ePWM register address space has been remapped for better alignment and easy usage.
Delayed Trip Functionality
Changes have been added to achieve Deadband insertion capabilities to support, for example, delayed trip functionality needed for peak current mode control type application scenarios. This has been accomplished by allowing comparator events to go into the Action Qualifier as a trigger event ( Events T1 and T2 ). If comparator T1 / T2 events are used to edit the PWM, changes to the PWM waveform will not take place immediately. Instead, they will synchronize to the next TBCLK.
Dead-Band Generator Submodule Enhancements
Shadowing of the DBCTL register to allow dynamic configuration changes.
One Shot and Global Load of Registers
The ePWM Type 4 allows one shot and global load capability from shadow to active registers to avoid partial loads in, for example, multi-phase applications. It also allows a programmable prescale of shadow to active load events. ePWM Type 4 Global Load can simplify ePWM software by removing interrupts and ensuring that all registers are loaded at the same time.
Trip Zone Submodule Enhancements
Independent flags have been added to reflect the trip status for each of the TZ sources. Changes have been made to the trip zone submodule to support certain power converter switching techniques like valley switching.
Digital Compare Submodule Enhancements
Blanking window filter register width has been increased from 8 to 16 bits. DCCAP functionality has been enhanced to provide more programmability.
PWM SYNC Related Enhancements
The ePWM Type 4 allows PWM SYNCOUT generation based on CMPC and CMPD events. These events can also be used for PWMSYNC pulse selection.
The ePWM Type 2 is fully compatible with Type 1. Type 2 has the following enhancements in addition to the Type 1 features:
High Resolution Dead-Band Capability
High-resolution capability is added to dead-band RED and FED in half-cycle clocking mode.
Dead-Band Generator Submodule Enhancements
The ePWM Type 2 has features to enable both RED and FED on either PWM output. Provides increased dead band with 14-bit counters and dead-band / dead-band high-resolution registers are shadowed
High Resolution Extension available on ePWMxB outputs
Provides the ability to enable high-resolution period and duty cycle control on ePWMxB outputs.
Counter Compare Submodule Enhancements
The ePWM Type 2 allows Interrupts and SOC events to be generated by additional counter compares CMPC and CMPD.
Event Trigger Submodule Enhancements
Prescaling logic to issue interrupt requests and ADC start of conversion expanded up to every 15 events. It allows software initialization of event counters on SYNC events.
Digital Compare Submodule Enhancements
Digital Compare Trip Select logic [DCTRIPSEL] has up to 12 external trip sources selected by the Input X-BAR logic in addition to an ability to OR all of them (up to 14 [external and internal sources]) to create the respective DCxEVTs.
Simultaneous Writes to TBPRD and CMPx Registers
This feature allows writes to TBPRD, CMPA: CMPAHR, CMPB: CMPBHR, CMPC and CMPD of any ePWM module to be tied to any other ePWM module, and also allows all ePWM modules to be tied to a particular ePWM module if desired.
Shadow to Active Load on SYNC of TBPRD and CMP Registers
This feature supports simultaneous writes of TBPRD and CMPA/B/C/D registers.
ePWM Electrical Data and Timing
ePWM Switching Characteristics
TBPRD Register (Offset = 63h) [reset = 0h]
TBPHS Register (Offset = 60h) [reset = 0h]
TBCTR Register (Offset = 4h) [reset = 0h]
TBCTL Register (Offset = 0h) [reset = 83h]
AQCTLA Register (Offset = 40h) [reset = 0h]
Final code
#include "F28x_Project.h"
#include "F2837xD_device.h"
#include "F2837xD_Examples.h"
#include "driverlib.h"
#include "device.h"
void EPWM_init();
void PinMux_init();
//
// Function Prototypes
//
void pwm_init();
void pwm_init_2();
void main(void)
{
//
// Initialize device clock and peripherals
//
Device_init();
//
// Disable pin locks and enable internal pull-ups.
//
Device_initGPIO();
//
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
//
Interrupt_initModule();
//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
//
Interrupt_initVectorTable();
//
// Configure ePWMs
//
PinMux_init();
// SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_GTBCLKSYNC);
SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
//
// Initialize ePWM1
//
pwm_init();
pwm_init_2();
// initEPWMWithoutDB(myEPWM1_BASE);
//
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
//
// Enable Global Interrupt (INTM) and real time interrupt (DBGM)
//
EINT;
ERTM;
//
// IDLE loop. Just sit and loop forever (optional):
//
while(1){
}
}
void pwm_init()
{
EPwm1Regs.TBPRD = 3000; // Set timer period 801 TBCLKs
EPwm1Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000;
// Set Compare values
EPwm1Regs.CMPA.bit.CMPA = 1500; // Set compare A value
// Setup counter mode
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
//
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on Zero
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;
}
void pwm_init_2()
{
EPwm2Regs.TBPRD = 5000; // Set timer period 801 TBCLKs
EPwm2Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm2Regs.TBCTR = 0x0000;
// Set Compare values
// EPwm1Regs.CMPB.bit.CMPB=1000; // Set compare A value
EPwm2Regs.CMPA.bit.CMPA = 3500; // Set compare A value
// Setup counter mode
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on Zero
EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;
}
void PinMux_init()
{
EALLOW;
GpioCtrlRegs.GPAPUD.bit.GPIO0 = 1; // Disable pull-up on GPIO0 (EPWM1A)
GpioCtrlRegs.GPAPUD.bit.GPIO2 = 1; // Disable pull-up on GPIO1 (EPWM1B)
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // Configure GPIO0 as EPWM1A
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // Configure GPIO1 as EPWM1B
EDIS;
}
Output Waveforms
