Deadband Control Using TMS320

Overview

A deadband or deadband (also known as a dead zone or a neutral zone) is a band of input values in the domain of a transfer function in a control system or signal processing system where the output is zero (the output is ‘dead’ – no action occurs). Deadband regions can be used in control systems such as servo amplifiers to prevent oscillation or repeated activation-deactivation cycles (called ‘hunting’ in proportional control systems). A form of deadband in mechanical systems, compound machines such as gear trains is a backlash.

Components required table

Software Requirements

1. Code Composer Studio
2. Logic Analyzer
3. Logic Analyzer Software 1.2.18

Purpose of the Dead-Band Submodule

• Programming signal pairs for:

1. – Active high (AH)
2. – Active low (AL)
3. – Active high complementary (AHC)
4. – Active low complementary (ALC)

• Adding programmable delay to rising edges (RED)
• Adding programmable delay to falling edges (FED)
• Can be totally bypassed from the signal path (note dotted lines in the diagram)

Dead-band Submodule Additional Operating Modes

On type 1 ePWM RED could appear on one channel output and FED could appear on the other channel output.

The following list shows the distinct difference between type 1 and types 4 modules with respect to deadband operating modes:

• •By adding S6, S7, and S8 in Figure 15-33, RED and FED can appear on both the A-channel and B-channel outputs. Additionally, both RED and FED together can be applied to either the A-channel or B-channel outputs to allow B-channel phase shifting with respect to the A-channel.

Note: Phase shifting B-channel with respect to the A-channel using the dead-band submodule

• The dead-band counters have also been increased to 14 bits
• Dead-band and dead-band High-resolution registers are now shadowed.
• High-resolution dead-band RED and FED have been enabled using the DBREDHR and DBFEDHR registers

Duty Cycle Control

Pulse transformer-based gate drive designs need to comprehend the magnetic properties or characteristics of the transformer and associated circuitry. Saturation is one such consideration. To assist the gate drive designer, the duty cycles of the second and subsequent pulses have been made

programmable. These sustaining pulses ensure the correct drive strength and polarity is maintained on the power switch gate during the on period, and hence a programmable duty cycle allows a design to be tuned or optimized via software control.

Figures 15-39 shows the duty cycle control that is possible by programming the CHPDUTY bits. One of

seven possible duty ratios can be selected ranging from 12.5% to 87.5%.

Figure 15-39. PWM Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining Pulses

ePWM Electrical Data and Timing

ePWM Timing Requirements

1. For an explanation of the input qualifier parameters
2. For SYSCLK above 100 MHz, the EPWMCLK must be half of SYSCLK.

High-Resolution Pulse Width Modulator (HRPWM)

The HRPWM combines multiple delay lines in a single module and a simplified calibration system by using a

dedicated calibration delay line. For each ePWM module, there are two HR outputs:

• • HR Duty and Deadband control on Channel A
• • HR Duty and Deadband control on Channel B
• The HRPWM module offers PWM resolution (time granularity) that is significantly better than what can be achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:
• Significantly extends the time resolution capabilities of conventionally derived digital PWM
• This capability can be used in both single-edge (duty cycle and phase-shift control) as well as dual-edge control for frequency/period modulation.

• Finer time granularity control or edge positioning is controlled through extensions to the Compare A, B,

phase, period and deadband registers of the ePWM module.

Note

The minimum HRPWMCLK frequency allowed for HRPWM is 60 MHz.

HRPWM Electrical Data and Timing

High-Resolution PWM Timing Requirements

For SYSCLK above 100 MHz, the EPWMCLK must be half of SYSCLK.

High-Resolution PWM Characteristics

Dead-Band Waveforms for Typical Cases (0% < Duty < 100%)

The dead-band submodule supports independent values for rising-edge (RED) and falling-edge (FED) delays. The amount of delay is programmed using the DBRED and DBFED registers. These are 10-bit registers and their value represents the number of the time-base clocks, TBCLK, periods by which a signal edge is delayed. For example, the formula to calculate falling-edge-delay and rising-edge-delay is:

FED = DBFED × TTBCLK

RED = DBRED × TTBCLK

Where TTBCLK is the period of TBCLK, the prescaled version of EPWMCLK.

For convenience, delay values for various TBCLK options are shown in Table 15-10. The ePWM input clock frequency that these delay values have been computed by is 100 MHz.

3-Phase Interleaved DC/DC Converter Waveforms

Configuring Hi-Res in Deadband Rising Edge and Falling Edge Delay

Once the ePWM has been configured to provide conventional PWM of a given frequency, polarity and deadband enabled in half cycle clocking mode, the high-resolution operation on dead-band RED and FED lines are enabled by programming the HRCNFG2 register in that particular ePWM module’s register space. This register provides the following configuration options:

Edge Mode — The MEP can be programmed to provide precise position control on the dead band rising edge (RED), dead band falling edge (FED) or both edges (rising edge of DBRED signal and falling edge of DBFED signal ) at the same time.

Control Mode — Selects the time event that loads the shadow value in the active register for DBRED and DBFED in high-resolution mode. The user needs to select the pulse to match the selection in the ePWM DBCTL[LOADREDMODE] & DBCTL[LOADFEDMODE] bits.

Deadband High-Resolution Operation

Assumptions for this example:

Deadband Delay Values as a Function of DBFED and DBRED:

Step 1: Integer Dead band value conversion for DBREDM register

Step 2: Fractional value conversion for Dead band high-resolution register DBREDHR

TBCTL Register (Offset = 0h) [reset = 83h]

Time Base Control Register

TBPRD Register (Offset = 63h) [reset = 0h]

Time Base Period Register

CMPCTL Register (Offset = 8h) [reset = 0h]

Counter Compare Control Register

AQCTLA Register (Offset = 40h) [reset = 0h]

Action Qualifier Control Register For Output A

DBCTL Register (Offset = Ch) [reset = 0h]

Dead-Band Generator Control Register

Final code

/*
 * main.c
 *
 *  Created on: 05-Apr-2022
 *      Author: Admin
 */



#include <stdio.h>
#include <string.h>
#include <stdlib.h>

#include "F2837xD_device.h"
#include "F28x_Project.h"
#include "F2837xD_Examples.h"

#include "device.h"
#include "driverlib.h"

void PinMux_init_1();
void initEPWM1();


void main(void)
{
    Device_init();
    Device_initGPIO();

    Interrupt_initModule();
    Interrupt_initVectorTable();
    PinMux_init_1();
    initEPWM1();


    while(1)
    {
        EPwm1Regs.CMPA.bit.CMPA = 200;    // Set compare A value

    }
}


void PinMux_init_1()
{
    EALLOW;
    //EPWM1 -> myEPWM1 Pinmux
    GpioCtrlRegs.GPAPUD.bit.GPIO0=0; //
    GpioCtrlRegs.GPAPUD.bit.GPIO1=0;

    GpioCtrlRegs.GPAMUX1.bit.GPIO0=1; // 0=GPIO,  1=EPWM1A,  2=Resv,  3=Resv
    GpioCtrlRegs.GPAMUX1.bit.GPIO1=1; // 0=GPIO,  1=EPWM1A,  2=Resv,  3=Resv

    EDIS;

}


void initEPWM1()
{
    // Disable sync(Freeze clock to PWM as well). GTBCLKSYNC is applicable
    // only for multiple core devices. Uncomment the below statement if
    // applicable.
    //
    // SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_GTBCLKSYNC);

    // Set Compare values

    //        // ------------ EPWM1A ------------------                            BUCK //

    EPwm1Regs.TBPRD = 1000;       // Set timer period 801 TBCLKs
    EPwm2Regs.TBPHS.bit.TBPHS = 0x0000;        // Phase is 0
    EPwm2Regs.TBCTR = 0x0000;

    EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;
    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
    EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;
    EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
    EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
    EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;


    EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;           // load on CTR = Zero
    EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

    EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;
    EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
    EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET;
    EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR;

    EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;

    EPwm1Regs.DBRED.all = 100;
    EPwm1Regs.DBFED.all = 100;

    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC=1;
    EDIS;
}

Output waveforms

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